To fulfill the high density package and wider channel bandwidth of the high speed integrated circuit (IC), a through-silicon via (TSV) plays an important role in the three dimension integrated circuit (3D ICs) technology. The TSV is a vertical electrical connection between chips, thereby reducing the length of connection lines greatly. Moreover, silicon interposers are also applied to the outside connection of the 3D ICs. The silicon interposers can provide two dimension (2D) connection line layers as well as connection lines between multiple chips laminated in a third dimension. When such 3D ICs are applied to a high speed digital device, the TSVs and the silicon interposers need to support wider bandwidth and be minimized, whereby the high speed digital device may have higher performance and a minimized size.
On the other hand, dielectric layers are used for isolating the TSVs from a silicon substrate. Because of the electric conductivity of the chip body, the dielectric layer and the chip body may cooperate to cause inevitable capacitance effect. The capacitance effect and the energy consumption of a silicon carrier in the 3D IC will cause the distortion or decay of high speed digital signal according to the changing of signal frequency. To preventing the decay of signals in the high speed signal transmission (e.g. 20 or 25 Gbps), equalizer circuits are designed to reduce the non-linear transmission loss.
Generally, a passive equalizer circuit requires resistance components and capacitance components. Such resistance components and capacitance components need extra material and fabrication processes in the design and manufacture of the 3D IC. Moreover, adding equalizer circuits in the 3D IC will increase the chip size and the manufacture cost and complicate the chip design.